1. Field of the Invention
The present invention generally relates to programmable logic devices. More specifically, the present invention relates to using blocks of tristate drivers within programmable logic devices.
2. Description of the Related Art
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to program particular logic functions the circuit will perform. Logic functions performed by small, medium, and large-scale integration integrated circuits can instead be performed by programmable logic devices. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform particular functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable devices as well as re-programmable devices.
Programmable logic encompasses all digital logic circuits that are configured by the end user, including PLDs, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). The general architecture of an embedded array programmable logic design will be generally familiar to those knowledgeable of the FLEX10Ko logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture, for example, is described in U.S. Pat. No. 5,550,782 and Altera Data Book 1996, both of which are incorporated herein by reference.
Referring initially to FIG. 1, a CPLD 100 with an embedded array programmable logic design will be described. Although only a few logic array blocks or memory blocks are illustrated, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
The CPLD 100 includes a plurality of logic array blocks (LAB) 110 and a plurality of embedded array blocks (EAB) 112. Each EAB 112 includes an array of memory elements. Each LAB 110 includes a plurality of logic elements LE 111 which are capable of performing simple logic functions.
As shown in FIG. 1, the plurality of LABs 110 and the plurality of EABs 112 are programmably interconnected by way of a plurality global horizontal conductors 114 and a plurality of global vertical conductors 116 to form a logic and memory array. The global horizontal conductors 114 couple to the horizontal ports 108, and the global vertical conductors 116 couple to the vertical ports 106.
Conventional logic elements LE 111 within the LABs 110 include combinational logic arranged to produce a variety of simple functions such as, for example, a data selector. A data selector operates to select a specific data word or data bit, which then forms an output signal, which drives an output line or bus.
FIG. 2 is a schematic diagram of a single bit data selector circuit formed by combinational logic. The single bit data selector circuit 130 includes an inverter 132, a first AND gate 134, a second AND gate 136, and an OR gate 138. The first AND gate 134 has a first input line 140 connected to an inverter input line 142 and a second input line 144 capable of receiving a first data bit A. The second AND gate has a first input line connected to an inverter output line 146 and a second input line 148 capable of receiving a second data bit B. An output line 150 from the first AND gate 134 and an output line 152 from the second AND gate 136 form a first input and a second input, respectively, to the OR gate 138. An output line 154 of the OR gate 138 carries an output signal OUT to external circuitry.
The single bit data selector circuit 130 operates as follows. A binary SELECT signal is supplied to the inverter input line 142. The binary SELECT signal causes either the first data bit A or the second data bit B to be passed to the output line 154 of the OR gate 138. By way of example, if the SELECT signal is a logical 1, the second AND gate 136 passes a logical 0 to the second input of the OR gate 138 and the first AND gate 134 passes the first data bit A to the first input of the OR gate 138. In this way, the first data bit A forms the output signal OUT. Alternatively, if the SELECT signal is a logical 0, the second data bit B forms the output signal OUT. Unfortunately, in order to accommodate data words having more than one data bit, the combinational logic structure required can become very complex such as when more sources are added such as a 4 to 1 and an 8 to 1 selector, for example.
In order to fit a desired logic function in the CPLD 100, various logic elements and/or memory blocks are individually configured to perform a small but crucial part of the overall logic and/or memory function. Any automatic place and route software such as, for example, MAX+PLUS II.TM. developed by the Altera Corporation of San Jose, Calif. must then logically connect all the programmed logic elements and/or memory blocks such that CPLD 100 may execute the desired logic function.
Unfortunately, when the LABs 110 (and associated logic elements LE 111) are distributed through-out the CPLD 100, fitting a desired logic function may result in substantial routing delays due to circuitous logical connections of the programmed logic elements and/or memory blocks. In certain cases, the logical connections of the programmed logic elements and/or memory blocks may be so circuitous as to create a slow data path, which may prove to be unacceptable for the application at hand. Additionally, the logical connections required to fit the logic function and/or memory-logic function typically require a substantial portion of limited routing resources available in the CPLD 100. In some instances, fitting the desired logic function requires more routing resources than are available in the CPLD 100, in which case, the fitting is said to have failed.
A tristate buffer is a device capable of operating so as to selectively produce binary logic states but also a third high impedance state known in the art as tristate mode. Tristate drivers coupled to a data bus (commonly referred to as a tristate bus) are capable of generating the same logic functions as can be generated by combinational logic.
FIG. 3 is schematic diagram of a four bit data selector circuit 160 formed by tristate drivers capable of selecting two data words. The four-bit data selector circuit 160 includes first tristate drivers 162-0 through 162-3 connected so as to be capable of supplying a selected first data word A (including data bits A.sub.0 -A.sub.3) to tristate data busses 172-0 through 172-3, respectively. In a similar manner, the four-bit data selector circuit 160 also includes second tristate drivers 164-0 through 164-3 connected so as to be capable of supplying a selected second data word B to the tristate data busses 172-0 through 172-3, respectively. The four bit data selector circuit 160 also includes a SELECT signal circuit 166, a first output enable (OE) circuit 168, a second output enable circuit 170. Each of the tristate drivers 162 has an output enable (OE) line 174, and input line 176, and an output line 178. Similarly, each of the tristate drivers 164 has an output enable (OE) line 180, and input line 182, and an output line 184.
The four-bit data selector circuit 160 operates as follows. The tristate drivers 162 associated with the first data word A are enabled when a select signal SELECT generated by select signal circuit 166 is sent to the first output enable (OE) circuit 168. In response, the first output enable (OE) circuit 168 generates an output enable (OE) signal. In conventional tristate logic circuits, contention between the tristate drivers 162-0 through 162-3 and tristate drivers 164-0 through 164-3 is avoided by first inverting the select signal SELECT to form a complementary select signal /SELECT. The complementary select signal /SELECT is then sent to the second output enable (OE) circuit 168. In response, the second output enable (OE) circuit 168 sends a complementary enable (i.e., disable signal) to each of the tristate drivers 164-0 through 164-3 by way of the output enable (OE) line 180 causing the tristate drivers 164-0 through 164-3 to go into a high impedance state (i.e., tristate mode). In this manner, each of the tristate drivers 162-0 through 162-3 pass a single data bit A.sub.0 through A.sub.3, respectively, to the associated output buffer 172-0 through 172-3 forming thereby the data word A (A.sub.0, A.sub.1, A.sub.2, A.sub.3). For the proper operation of the four-bit data selector circuit 160, it is therefore essential that each of the tristate drivers 164-0 through 164-3 associated with the unselected data word (data word B) be in the tristate mode.
Unfortunately, the four bit data selector circuit 160 could suffer from tristate driver contention caused by line skew related to different lengths of the signal paths between, for example, the first OE signal circuit 168 and the first tristate drivers 162 and the second OE circuit 170 and the second tristate drivers 164. If, for example, the signal paths between the first OE signal circuit 168 and the first tristate drivers 162 is different then the signal paths between the second OE circuit 170 and the second tristate drivers 164, the resulting line skew may cause both the tristate drivers 162 and 164 to drive tristate bus 172 when the SELECT signal transitions. If the difference in the timing of the two paths is large, the time duration that both drivers 162 and 164 are enabled may become appreciable and driver contention may result. It is for this reason, that the circuit must be designed with minimal line skew.
Consequently, when implemented in a PLD, the four bit data selector circuit 160 lacks layout flexibility because associated tristate drivers must be spatially arranged together. Hence, by sacrificing (place and route) flexibility, a logic function using tristate buffers coupled to a tristate data bus can be fit to a PLD such that the logic design does not suffer from slow data paths by locating the tristate drivers in the same proximate location as the tristate bus. However, the resulting loss in flexibility hinders the ability to (place and route) (efficiently and otherwise) other components of the circuit design.
In view of the foregoing, it is advantageous and therefore desirable to have available a programmable logic device that incorporates tristate buffers so that routing flexibility in PLDs can be maintained even when circuit designs include tristate logic.